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rev 1.1 data sheet no. pd60300-a irmcf312 dual channel sensorless motor control ic for appliances features ? mce tm (motion control engine) - hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet ac motor ? integrated power factor correction control ? supports both interior and surface permanent magnet motors ? built-in hardware peripheral for single shunt current feedback reconstruction ? no external current or voltage sensing operational amplifier required ? dual channel three/two-phase space vector pwm ? three-channel analog output (pwm) ? embedded 8-bit high speed microcontroller (8051) for flexible i/o and man-machine control ? jtag programming port for emulation/debugger ? two serial communication interface (uart) ? i 2 c/spi serial interface ? watchdog timer with independent analog clock ? three general purpose timers/counters ? two special timers: periodi c timer, capture timer ? external eeprom and internal ram facilitate debugging and code development ? pin compatible with irmck312, otp-rom version ? 1.8v/3.3v cmos product summary maximum crystal frequency 60 mhz maximum internal clock (sysclk) frequency 128 mhz sensorless control computation time 11 sec typ mce tm computation data range 16 bit signed program ram loaded from external eeprom 48k bytes data ram 8k bytes gatekill latency (digital filtered) 2 sec pwm carrier frequency counter 16 bits/ sysclk a/d input channels 11 a/d converter resolution 12 bits a/d converter conversion speed 2 sec 8051 instruction execution speed 2 sysclk analog output (pwm) resolution 8 bits uart baud rate (typ) 57.6k bps number of i/o (max) 36 package (lead-free) qfp100 description irmcf312 is a high performance ram based motion control ic designed primarily for appliance applications. irmcf312 is designed to achieve low cost and high per formance control solutions for advanced inverterized appliance motor control. irmcf312 contains two computation engi nes. one is motion control engine (mce tm ) for sensorless control of permanent magnet motors; the other is an 8-bit hi gh-speed microcontroller (8051). both com putation engines are integrated into one monolithic chip. the mce tm contains a collection of control elements such as proportional plus integral, vector rotator, angle estimator, multiply/divide, low loss svpwm, single shunt ifb. t he user can program a moti on control algorithm by connecting these control elements using a graphic compiler. key components of t he sensorless control al gorithms, such as the angle estimator, are provided as complete pre-defined control blocks impl emented in hardware. a unique analog/digital circuit and algorithm to fully support single shunt current rec onstruction is also provided. the 8051 microcontroller performs 2- cycle instruction execution (60mips at 120mhz). the mce and 8051 microcontrolle r are connected via dual port ram to process signal monitoring and command input. an advanced graphic compiler for the mce tm is seamlessly integrated into the matlab/simulink environment, while third party jtag bas ed emulator tools are s upported for 8051 developments. irmcf312 comes with a small qfp100 pin lead-free package.
irmcf312 2 table of contents 1 overview..................................................................................................................... ................. 4 2 irmcf312 block diagram and main functions ........................................................................ 5 3 pinout....................................................................................................................... .................... 7 4 input/output of irmcf312..................................................................................................... .... 8 4.1 8051 peripheral interface group........................................................................................... 9 4.2 motion peripheral interface group ..................................................................................... 10 4.3 analog interface group ..................................................................................................... . 11 4.4 power interface group ...................................................................................................... .. 12 4.5 test interface............................................................................................................. .......... 12 5 application connections ...................................................................................................... ..... 13 6 dc characteristics ........................................................................................................... .......... 14 6.1 absolute maximum ratings ............................................................................................... 14 6.2 system clock frequency and power consumption............................................................ 14 6.3 digital i/o dc characteristics............................................................................................ 15 6.4 pll and oscillator dc characteristics............................................................................... 16 6.5 analog i/o dc characteristics ........................................................................................... 16 6.6 analog i/o dc characteristics ........................................................................................... 17 6.7 under voltage lockout dc characteristics ....................................................................... 18 6.8 cmext and aref characteristics.................................................................................... 18 7 ac characteristics ........................................................................................................... .......... 19 7.1 pll ac characteristics ..................................................................................................... . 19 7.2 analog to digital converter ac characteristics ................................................................ 20 7.3 op amp ac characteristics ............................................................................................... 21 7.4 op amp ac characteristics ............................................................................................... 21 7.5 sync to svpwm and a/d conversion ac timing......................................................... 22 7.6 gatekill to svpwm ac timing.................................................................................. 23 7.7 interrupt ac timing ........................................................................................................ ... 23 7.8 i 2 c ac timing .................................................................................................................... 24 7.9 spi ac timing.............................................................................................................. ...... 25 7.9.1 spi write ac timing .................................................................................................... 25 7.9.2 spi read ac timing.................................................................................................... 26 7.10 uart ac timing ........................................................................................................... 27 7.11 capture input ac timing .......................................................................................... 28 7.12 jtag ac timing ............................................................................................................ 29 8 pin list..................................................................................................................... .................. 30 9 package dimensions........................................................................................................... ....... 34 10 part marking information.................................................................................................... ... 35
irmcf312 3 table of figures figure 1. typical application block diagram using irmcf312.................................................. 4 figure 2. irmcf312 internal block diagram ................................................................................ 5 figure 3. irmcf312 pin configuration ......................................................................................... 7 figure 4. input/output of irmcf312 ............................................................................................ . 8 figure 5. application connection of irmcf312 ......................................................................... 13 figure 6. clock frequency vs. power consumption..................................................................... 14 table of tables table 1. absolute maximum ratings............................................................................................ 14 table 2. system clock frequency............................................................................................... .. 14 table 3. digital i/o dc characteristics ....................................................................................... . 15 table 4. pll dc characteristics ............................................................................................... ... 16 table 5. analog i/o dc characteristics ....................................................................................... 16 table 6. analog i/o dc characteristics ....................................................................................... 17 table 7. uvcc dc characteristics .............................................................................................. .. 18 table 8. cmext and aref dc characteristics.......................................................................... 18 table 9. pll ac characteristics ............................................................................................... ... 19 table 10. a/d converter ac characteristics................................................................................ 20 table 11. current sensing op amp ac characteristics............................................................... 21 table 12. voltage sensing op amp ac characteristics............................................................... 21 table 13. sync ac characteristics............................................................................................. 22 table 14. gatekill to svpwm ac timing ............................................................................ 23 table 15. interrupt ac timing................................................................................................. ..... 23 table 16. i 2 c ac timing .............................................................................................................. 24 table 17. spi write ac timing................................................................................................. ... 25 table 18. spi read ac timing.................................................................................................. ... 26 table 19. uart ac timing...................................................................................................... ... 27 table 20. capture ac timing ................................................................................................. 28 table 21. jtag ac timing...................................................................................................... .... 29 table 22. pin list ............................................................................................................ .............. 33
irmcf312 4 1 overview irmcf312 is a new international rectifier integrat ed circuit device primarily designed as a one- chip solution for complete inverter controlled appliance dual motor control applications. unlike a traditional microcontroller or dsp, the irmcf312 provides a built-in closed loop sensorless control algorithm using the unique motion control engine (mce tm ) for permanent magnet motors. the mce tm consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port ram to map internal signal nodes. irmcf312 also employs a unique single shunt current reconstructi on circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the ic. the sensorless control is the same for both motors with a single shunt current sensing capability. motion control programming is achieved using a dedicated graphical comp iler integrated into the matlab/simulink tm development environment. sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. the 8051 microcontroller is equipped with a jtag port to facilitate emulation and debugging tools. figure 1 shows a typical application schematic using irmcf312. irmcf312 is intended for development purpose and contains 48k bytes of ram, which can be loaded from external eeprom for 8051 pr ogram execution. for high volume production, irmck312 contains otp rom in place of progr am ram to reduce the cost. both irmcf312 and irmck312 come in the same 100-pin qfp p ackage with identical pin configuration to facilitate pc board layout and transition to mass production figure 1. typical applicati on block diagram using irmcf312
irmcf312 5 2 irmcf312 block diagram and main functions irmcf312 block diagram is shown in figure 2. 8bit up address/data bus motion control bus figure 2. irmcf312 internal block diagram irmcf312 contains the following functions for sensorless ac motor control applications: ? motion control engine (mce tm ) o proportional plus integral block o low pass filter o differentiator and lag (high pass filter) o ramp o limit o angle estimate (sensorless control) o inverse clark transformation o vector rotator o bit latch
irmcf312 6 o peak detect o transition o multiply-divide (signed and unsigned) o divide (signed and unsigned) o adder o subtractor o comparator o counter o accumulator o switch o shift o atan (arc tangent) o function block (any curve fitting, nonlinear function) o 16-bit wide logic operations (and, or, xor, not, negate) o mce tm program and data memory (6k byte). note 1 o mce tm control sequencer ? 8051 microcontroller o three 16-bit timer/counters o 16-bit periodic timer o 16-bit analog watchdog timer o 16-bit capture timer o up to 36 discrete i/os o eleven-channel 12-bit a/d ? five buffered channels (0 ? 1.2v input) ? six unbuffered channels (0 ? 1.2v input) o jtag port (4 pins) o up to three channels of analog output (8-bit pwm) o two uart o i 2 c/spi port o 48k byte program ram loaded from external eeprom o 2k byte data ram. note 1 note 1: total size of ram is 8k byte including mce program, mce data, and 8051 data. different sizes can be allocated depending on applications.
irmcf312 7 3 pinout figure 3. irmcf312 pin configuration attention : pin 51 must be left floating. do not connect.
irmcf312 8 4 input/output of irmcf312 all i/o signals of irmcf312 are shown in figure 4. all i/o pins are 3.3v logic interface except a/d interface pins. figure 4. input/output of irmcf312
irmcf312 9 4.1 8051 peripheral interface group uart interface p1.1/rxd input, receive data to irmcf312, can be configured as p1.1 p1.2/txd output, transmit data from irmcf312, can be configured as p1.2 p3.6/rxd1 input, 2 nd channel receive data to irmcf312, can be configured as p3.6 p3.7/txd1 output, 2 nd channel transmit data from irmcf312, can be configured as p3.7 discrete i/o interface p1.0/t2 input/output port 1.0, can be c onfigured as timer/counter 2 input p1.3/sync/sck input/output port 1.3, can be c onfigured as sync output or spi clock, needs to be pulled up to vdd1 in order to boot from i 2 c eeprom p1.4/cap input/output port 1.4, can be c onfigured as capture timer input p1.5 input/output port 1.5 p1.6 input/output port 1.6 p1.7 input/output port 1.7 p2.0/nmi input/output port 2.0, can be configured as non-maskable interrupt p2.1 input/output port 2.1 p2.2 input/output port 2.2 p2.3 input/output port 2.3 p2.4 input/output port 2.4 p2.5 input/output port 2.5 p3.0/int2/cs1 input/output port 3.0, can be conf igured as external interrupt 2 or spi chip select 1 p3.2/int0 input/output port 3.2, can be configured as external interrupt 0 p3.3/int1 input/output port 3.3, can be configured as external interrupt 1 p3.4/t0 input/output port 3.4, can be c onfigured as timer/counter 0 input p3.5/t1 input/output port 3.5, can be c onfigured as timer/counter 1 input p4.0/int3 input/output port 4.0, can be configured as external interrupt 3 p4.1/int4 input/output port 4.1, can be configured as external interrupt 4 p4.2/int5 input/output port 4.2, can be configured as external interrupt 5 p4.3/int6 input/output port 4.3, can be configured as external interrupt 6 p4.4/int7 input/output port 4.4, can be configured as external interrupt 7 p4.5/int8 input/output port 4.5, can be configured as external interrupt 8 p4.6/int9 input/output port 4.6, can be configured as external interrupt 9 p4.7/int10 input/output port 4.7, can be configured as external interrupt 10 p5.0/pfcgkill input/output port 5.0, can be configured as pfcgkill p5.1/tms input/output port 5.1, can be configured as jtag tms pin p5.2/tdo input/output port 5.2, can be configured as jtag tdo pin p5.3/tdi input/output port 5.3, can be configured as jtag tdi pin
irmcf312 10 analog output interface p2.6/aopwm0 input/output, can be configured as 8-bit pwm output 0 with programmable carrier frequency p2.7/aopwm1 input/output, can be configured as 8-bit pwm output 1 with programmable carrier frequency p3.1/aopwm2 input/output, can be configured as 8-bit pwm output 2 with programmable carrier frequency crystal interface xtal0 input, connected to crystal xtal1 output, connected to crystal reset interface reset inout, system reset, needs to be pulled up to vdd1 but doesn?t require external rc time constant i 2 c/spi interface scl/so-si output, i 2 c clock output, spi so-si sda/cs0 input/output, i 2 c data line, chip select 0 of spi p3.0/int2/cs1 input/output port 3.0, can be conf igured as external interrupt 2 or spi chip select 1 p1.3/sync/sck input/output port 1.3, can be c onfigured as sync output or spi clock, needs to be pulled up to vdd1 in order to boot from i 2 c eeprom 4.2 motion peripheral interface group pwm cpwmuh output, motor 1 pwm phase u high side gate signal cpwmul output, motor 1 pwm phase u low side gate signal cpwmvh output, motor 1 pwm phase v high side gate signal cpwmvl output, motor 1 pwm phase v low side gate signal cpwmwh output, motor 1 pwm phase w high side gate signal cpwmwl output, motor 1 pwm phase w low side gate signal fpwmuh output, motor 2 pwm phase u high side gate signal fpwmul output, motor 2 pwm phase u low side gate signal fpwmvh output, motor 2 pwm phase v high side gate signal fpwmvl output, motor 2 pwm phase v low side gate signal fpwmwh output, motor 2 pwm phase w high side gate signal fpwmwl output, motor 2 pwm phase w low side gate signal pfcpwm output, pfc pwm
irmcf312 11 fault cgatekill input, upon assertion, this negates all six pwm signals for motor 1, programmable logic sense p5.0/pfcgkill input, upon assertion, this nega tes pfcpwm signal, programmable logic sense, can be configured as discrete i/o in which case cgatekill negates pfcpwm fgatekill input, upon assertion, this negates all six pwm signals for motor 2, programmable logic sense 4.3 analog interface group avdd analog power (1.8v) avss analog power return aref buffered 0.6v output cmext unbuffered 0.6v, input to the aref buffer, capacitor needs to be connected. ifbc+ input, operational amplifier positive input for shunt resistor current sensing of motor 1 ifbc- input, operational amplifier negative input for shunt resistor current sensing of motor 1 ifbco output, operational amplifier output for shunt resistor current sensing of motor 1 ifbf+ input, operational amplifier positive input for shunt resistor current sensing of motor 2 ifbf- input, operational amplifier negative input for shunt resistor current sensing of motor 2 ifbfo output, operational amplifier output for shunt resistor current sensing of motor 2 ipfc+ input, operational amplifier positive input for pfc current sensing ipfc- input, operational amplifier negative input for pfc current sensing ipfo output, operational amplifier output for pfc current sensing vac+ input, operational amplifier positive input for pfc ac voltage sensing vac- input, operational amplifier negative input for pfc ac voltage sensing vaco output, operational amplifier output for pfc ac voltage sensing vdc+ input, operational amplifier positive input for dc bus voltage sensing vdc- input, operational amplifier negative input for dc bus voltage sensing ain0/vdco input/output, analog input channe l 0 or operational amplifier output for dc bus voltage sensing ain1 input, analog input channel 1 (0-1.2v), needs to be pulled down to avss if unused ain2 input, analog input channel 2 (0-1.2v), needs to be pulled down to avss if unused
irmcf312 12 ain3 input, analog input channel 3 (0-1.2v), needs to be pulled down to avss if unused ain4 input, analog input channel 4 (0-1.2v), needs to be pulled down to avss if unused ain5 input, analog input channel 5 (0-1.2v), needs to be pulled down to avss if unused ain6 input, analog input channel 6 (0-1.2v), needs to be pulled down to avss if unused 4.4 power interface group vdd1 digital power for i/o (3.3v) vdd2 digital power for core logic (1.8v) vss digital common pllvdd pll power (1.8v) pllvss pll ground return 4.5 test interface tstmod must be tied to vss, used only for factory testing. p5.3/tdi input, jtag test data input p5.1/tms input, jtag test mode select tck input, jtag test clock p5.2/tdo output, jtag test data output
irmcf312 13 5 application connections typical application connection is shown in figure 5. all components necessary to implement a complete sensorless drive control algorithm are shown connected to irmcf312. figure 5. application connection of irmcf312
irmcf312 14 6 dc characteristics 6.1 absolute maximum ratings symbol parameter min typ max condition v dd1 supply voltage -0.3 v - 3.6 v respect to vss v dd2 supply voltage -0.3 v - 1.98 v respect to vss v ia analog input voltage -0.3 v - 1.98 v respect to avss v id digital input voltage -0.3 v - 3.65 v respect to vss t a ambient temperature -40 ? c - 85 ? c t s storage temperature -65 ? c - 150 ? c table 1. absolute maximum ratings caution: stresses beyond those listed in ?absolut e maximum ratings? may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 6.2 system clock frequency and power consumption symbol parameter min typ max unit sysclk system clock 32 - 128 mhz table 2. system clock frequency figure 6. clock frequency vs. power consumption 0 40 80 120 160 200 240 0 50 100 150 clock frequency (mhz) power (mw) vdd2 (1.8v) vdd1 (3.3v) total
irmcf312 15 6.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3.0 v 3.3 v 3.6 v recommended v dd2 supply voltage 1.62 v 1.8 v 1.98 v recommended v il input low voltage -0.3 v - 0.8 v recommended v ih input high voltage 2.0 v 3.6 v recommended c in input capacitance - 3.6 pf - (1) i l input leakage current 10 na 1 a v o = 3.3 v or 0 v i ol1 (2) low level output current 8.9 ma 13.2 ma 15.2 ma v ol = 0.4 v (1) i oh1 (2) high level output current 12.4 ma 24.8 ma 38 ma v oh = 2.4 v (1) i ol2 (3) low level output current 17.9 ma 26.3 ma 33.4 ma v ol = 0.4 v (1) i oh2 (3) high level output current 24.6 ma 49.5 ma 81 ma v oh = 2.4 v (1) table 3. digital i/o dc characteristics note: (1) data guaranteed by design. (2) applied to scl/so-si, sda/cs0 pins. (3) applied to p1.0/t2, p1.1/rxd, p1.2/txd, p1.3/sync/sck, p1.4/cap, p1.5, p1.6, p1.7, p2.0/nmi, p2.1, p2.2, p2.3, p2.4, p2.5, p2.6/aopwm0, p2.7/aopwm1, p3.0/int2/cs1, p3.1/aopwm2, p3.2/int0, p3.3/int1, p3.4/ t0, p3.5/t1, p3.6/rxd1, p3.7/txd1, p4.0/int3, p4.1/int4, p4.2/int5, p4.3/in t6, p4.4/int7, p4.5/int8, p4.6/int9, p4.7/int10, p5.0/pfcgkill, p5.1/tms, p5.2/tdo, p5.3/tdi, cgatekill, fgatekill, cpwmul, cpwmuh, cpwmvl, cpwmvh, cpwmwl, cpwmwh, fpwmul, fpwmuh, fpwmvl, fpwmvh, fpwmwl, fpwmwh, and pfcpwm pins.
irmcf312 16 6.4 pll and oscillator dc characteristics symbol parameter min typ max condition v pllvdd supply voltage 1.62 v 1.8 v 1.92 v recommended v il osc oscillator input low voltage v pllvss - 0.2* v pllvdd v pllvdd = 1.8 v (1) v ih osc oscillator input high voltage 0.8* v pllvdd v pllvdd v pllvdd = 1.8 v (1) table 4. pll dc characteristics note: (1) data guaranteed by design. 6.5 analog i/o dc characteristics - op amps for current sensing (ifbc+, ifbc-, ifbco, ifbf+, ifbf-, ifbfo, ipfc+, ipfc-, ipfco) c aref = 1nf, c mext = 100nf. unless specified, ta = 25 ? c. symbol parameter min typ max condition v avdd supply voltage 1.71 v 1.8 v 1.89 v recommended v offset input offset voltage - - 26 mv v avdd = 1.8 v v i input voltage range 0 v 1.2 v recommended v outsw op amp output operating range 50 mv (1) - 1.2 v v avdd = 1.8 v c in input capacitance - 3.6 pf - (1) r fdbk op amp feedback resistor 5 k - 20 k requested between op amp output and negative input op gaincl operating close loop gain 80 db - - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 1 ma - v out = 0.6 v (1) i snk op amp output sink current - 100 a - v out = 0.6 v (1) table 5. analog i/o dc characteristics note: (1) data guaranteed by design.
irmcf312 17 6.6 analog i/o dc characteristics - op amps for voltage sensing (vac+,vac-,vaco, vdc+, vdc-, vdco) c aref = 1nf, c mext = 100nf. unless specified, ta = 25 ? c. symbol parameter min typ max condition v avdd supply voltage 1.71 v 1.8 v 1.89 v v offset input offset voltage - - 26 mv v avdd = 1.8 v v i input voltage range 0 v 1.2 v v outsw op amp output operating range 50 mv (1) - 1.2 v v avdd = 1.8 v c in input capacitance - 3.6 pf - (1) op gaincl operating close loop gain 80 db - - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 5 ma - v out = 0.6 v (1) i snk op amp output sink current - 500 a - v out = 0.6 v (1) table 6. analog i/o dc characteristics note: (1) data guaranteed by design.
irmcf312 18 6.7 under voltage lockout dc characteristics - based on avdd (1.8v) unless specified, ta = 25 ? c. symbol parameter min typ max condition uv cc+ uvcc positive going threshold 1.53 v 1.66 v 1.71 v v dd1 = 3.3 v uv cc- uvcc negative going threshold 1.52 v 1.62 v 1.71 v v dd1 = 3.3 v uv cc h uvcc hysteresys - 40 mv - table 7. uvcc dc characteristics 6.8 cmext and aref characteristics c aref = 1nf, c mext = 100nf. unless specified, ta = 25 ? c. symbol parameter min typ max condition v cm cmext voltage 495 mv 600 mv 700 mv v avdd = 1.8 v v aref buffer output voltage 495 mv 600 mv 700 mv v avdd = 1.8 v v o load regulation (v dc - 0.6) - 1 mv - (1) psrr power supply rejection ratio - 75 db - (1) table 8. cmext and aref dc characteristics note: (1) data guaranteed by design.
irmcf312 19 7 ac characteristics 7.1 pll ac characteristics symbol parameter min typ max condition f clkin crystal input frequency 3.2 mhz 4 mhz 60 mhz (1) (see figure below) f pll internal clock frequency 32 mhz 50 mhz 128 mhz (1) f lwpw sleep mode output frequency f clkin 256 - - (1) j s short time jitter - 200 psec - (1) d duty cycle - 50 % - (1) t lock pll lock time - - 500 sec (1) table 9. pll ac characteristics note: (1) data guaranteed by design. xtal r 1 =1m r 2 =10 c 1 =30pf c 2 =30pf
irmcf312 20 7.2 analog to digital converter ac characteristics unless specified, ta = 25 ? c. symbol parameter min typ max condition t conv conversion time - - 2.05 sec (1) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 lsb (see figure below) table 10. a/d converter ac characteristics note: (1) data guaranteed by design. t hold voltage droop t sample s/h voltage input voltage
irmcf312 21 7.3 op amp ac characteristics - op amps for current sensing (ifbc+, ifbc-, ifbco, ifbf+, ifbf-, ifbfo, ipfc+, ipfc-, ipfco) unless specified, ta = 25 ? c. symbol parameter min typ max condition op sr op amp slew rate - 10 v/ sec - v avdd = 1.8 v, cl = 33 pf (1) op imp op input impedance - 10 8 ? - (1) t set settling time - 400 ns - v avdd = 1.8 v, cl = 33 pf (1) table 11. current sensing op amp ac characteristics note: (1) data guaranteed by design. 7.4 op amp ac characteristics - op amps for voltage sensing (vac+,vac-,vaco, vdc+, vdc-, vdco) unless specified, ta = 25 ? c. symbol parameter min typ max condition op sr op amp slew rate 2.5 v/ sec - v avdd = 1.8 v, cl = 33 pf (1) op imp op input impedance - 10 8 ? - (1) t set settling time 650 ns v avdd = 1.8 v, cl = 33 pf (1) table 12. voltage sensing op amp ac characteristics note: (1) data guaranteed by design.
irmcf312 22 7.5 sync to svpwm and a/d conversion ac timing sync iu,iv,iw t wsync t dsync1 ainx t dsync2 pwmux,pwmvx,pwmwx t dsync3 unless specified, ta = 25 ? c. symbol parameter min typ max unit t wsync sync pulse width - 32 - sysclk t dsync1 sync to current feedback conversion time - - 100 sysclk t dsync2 sync to ain0-6 analog input conversion time - - 200 sysclk (1) t dsync3 sync to pwm output delay time - - 2 sysclk table 13. sync ac characteristics note: (1) ain1 through ain6 channels are converted once every 6 sync events
irmcf312 23 7.6 gatekill to svpwm ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wgk gatekill pulse width 32 - - sysclk t dgk gatekill to pwm output delay - - 100 sysclk table 14. gatekill to svpwm ac timing 7.7 interrupt ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wint int0, int1 interrupt assertion time 4 - - sysclk t dint int0, int1 latency - - 4 sysclk table 15. interrupt ac timing
irmcf312 24 7.8 i 2 c ac timing scl sda t i2st1 t i2st2 t i2wsetup t i2clk t i2whold t i2rsetup t i2rhold t i2clk t i2en1 t i2en2 unless specified, ta = 25 ? c. symbol parameter min typ max unit t i2clk i 2 c clock period 10 - 8192 sysclk t i2st1 i 2 c sda start time 0.25 - - t i2clk t i2st2 i 2 c scl start time 0.25 - - t i2clk t i2wsetup i 2 c write setup time 0.25 - - t i2clk t i2whold i 2 c write hold time 0.25 - - t i2clk t i2rsetup i 2 c read setup time i 2 c filter time (1) - - sysclk t i2rhold i 2 c read hold time 1 - - sysclk table 16. i 2 c ac timing note: (1) i 2 c read setup time is determined by the programmable filter time applied to i 2 c communication.
irmcf312 25 7.9 spi ac timing 7.9.1 spi write ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csdelay cs to data delay time - - 10 nsec t wrdelay clk falling edge to data delay time - - 10 nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 17. spi write ac timing
irmcf312 26 7.9.2 spi read ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csrd cs to data delay time - - 10 nsec t rdsu spi read data setup time 10 - - nsec t rdhold spi read data hold time 10 - - nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 18. spi read ac timing
irmcf312 27 7.10 uart ac timing txd rxd data and parity bit start bit t baud stop bit t uartfil unless specified, ta = 25 ? c. symbol parameter min typ max unit t baud baud rate period - 57600 - bit/sec t uartfil uart sampling filter period (1) - 1/16 - t baud table 19. uart ac timing note: (1) each bit including start and stop bit is sampled th ree times at center of a bit at an interval of 1/16 t baud . if three sampled values do not agree, then uart noise error is generated.
irmcf312 28 7.11 capture input ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t capclk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register latch time - - 4 sysclk t cldelay capture rising edge to capture register latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 20. capture ac timing
irmcf312 29 7.12 jtag ac timing tck tdo t jhigh t jclk t co t jlow t jsetup t jhold tdi/tms unless specified, ta = 25 ? c. symbol parameter min typ max unit t jclk tck period - - 50 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to tdo propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 21. jtag ac timing
irmcf312 30 8 pin list pin number pin name internal ic pull-up /pull-down pin type description 1 xtal0 i crystal input 2 xtal1 o crystal output 3 p1.0/t2 i/o discrete progra mmable i/o or timer/counter 2 input 4 p1.1/rxd i/o discrete progra mmable i/o or uart receive input 5 p1.2/txd i/o discrete programmable i/o or uart transmit output 6 p1.3/sync/ sck i/o discrete programmable i/o or sync output or spi clock output, needs to be pulled up to vdd1 in order to boot from i 2 c eeprom 7 p1.4/cap i/o discrete programma ble i/o or capture timer input 8 p1.5 i/o discrete programmable i/o 9 p1.6 i/o discrete programmable i/o 10 p1.7 i/o discrete programmable i/o 11 p4.3/int6 i/o discrete programmable i/o or interrupt 6 12 p4.7/int10 i/o discrete programmable i/o or interrupt 10 13 vdd2 p 1.8v digital power 14 vss p digital common 15 vdd1 p 3.3v digital power 16 fgatekill i fan pwm shutdown input, 2- sec digital filter, configurable either high or low true. 17 fpwmwl 70 k ? pull up o fan pwm gate drive for phase w low side, configurable either high or low true 18 fpwmwh 70 k ? pull up o fan pwm gate drive for phase w high side, configurable either high or low true 19 fpwmvl 70 k ? pull up o fan pwm gate drive for phase v low side, configurable either high or low true 20 fpwmvh 70 k ? pull up o fan pwm gate drive for phase v high side, configurable either high or low true 21 fpwmul 70 k ? pull up o fan pwm gate drive for phase u low side, configurable either high or low true 22 fpwmuh 70 k ? pull up o fan pwm gate drive for phase u high side, configurable either high or low true 23 p2.0/nmi i/o discrete programmable i/o or non maskable interrupt 24 p2.1 i/o discrete programmable i/o 25 p2.2 i/o discrete programmable i/o 26 p2.3 i/o discrete programmable i/o
irmcf312 31 pin number pin name internal ic pull-up /pull-down pin type description 27 p2.4 i/o discrete programmable i/o 28 p2.5 i/o discrete programmable i/o 29 p2.6/ aopwm0 i/o discrete programmable i/o or analog output 0 (pwm) 30 p2.7/ aopwm1 i/o discrete programmable i/o or analog output 1 (pwm) 31 vdd2 p 1.8v digital power 32 vss p digital common 33 vss p digital common 34 vdd1 p 3.3 v digital power 35 p4.0/int3 i/o discrete programmable i/o or interrupt 3 36 p4.4/int7 i/o discrete programmable i/o or interrupt 7 37 ifbf- i fan single shunt current sensing op amp input (-) 38 ifbf+ i fan single shunt current sensing op amp input (+) 39 ifbfo o fan single shunt current sensing op amp output 40 ain0/vdco o analog input channe l 0 or dc bus voltage sensing op amp output 41 vdc+ i dc bus voltage sensing op amp input (+) 42 vdc- i dc bus voltage sensing op amp input (-) 43 avdd p analog power (1.8v) 44 avss p analog common 45 ain1 i analog input channel 1, 0-1.2v range, needs to be pulled down to avss if unused 46 cmext o unbuffered analog reference voltage output (0.6v) 47 aref o analog reference voltage output (0.6v) 48 ifbc- i compressor single shunt current sensing op amp input (-) 49 ifbc+ i compressor single shunt current sensing op amp input (+) 50 ifbco o compressor single shunt current sensing op amp output 51 dnc - do not connect. 52 ain2 i analog input channel 2, 0-1.2v range, needs to be pulled down to avss if unused 53 ain3 i analog input channel 2, 0-1.2v range, needs to be pulled down to avss if unused 54 ain4 i analog input channel 2, 0-1.2v range, needs to be pulled down to avss if unused 55 ain5 i analog input channel 2, 0-1.2v range, needs to be pulled down to avss if unused
irmcf312 32 pin number pin name internal ic pull-up /pull-down pin type description 56 ain6 i analog input channel 2, 0-1.2v range, needs to be pulled down to avss if unused 57 vac+ i ac input voltage sensing op amp input (+) 58 vac- i ac input voltage sensing op amp input (-) 59 vaco o ac input voltage sensing op amp output 60 ipfco o pfc shunt current sensing op amp output 61 ipfc+ i pfc shunt current sensing op amp input (+) 62 ipfc- i pfc shunt current sensing op amp input (-) 63 p4.5/int8 i/o discrete programmable i/o or interrupt 8 64 p4.1/int4 i/o discrete programmable i/o or interrupt 4 65 vdd2 p 1.8 v digital power 66 vss p digital common 67 vdd1 p 3.3v digital power 68 cgatekill i compressor pwm shutdown input, 2- sec digital filter, configurable either high or low true. 69 cpwmwl 70 k ? pull up o compressor pwm gate drive for phase w low side, configurable either high or low true 70 cpwmwh 70 k ? pull up o compressor pwm gate drive for phase w high side, configurable either high or low true 71 cpwmvl 70 k ? pull up o compressor pwm gate drive for phase v low side, configurable either high or low true 72 cpwmvh 70 k ? pull up o compressor pwm gate drive for phase v high side, configurable either high or low true 73 cpwmul 70 k ? pull up o compressor pwm gate drive for phase u low side, configurable either high or low true 74 cpwmuh 70 k ? pull up o compressor pwm gate drive for phase u high side, configurable either high or low true 75 p3.0/int2/ cs1 i/o discrete programmable i/o or int2 digital input or spi chip select 1 76 p5.0/ pfcgkill i discrete programmable i/o or pfc pwm shutdown input, 2- sec digital filter, configurable either high or low true. 77 pfcpwm 70 k ? pull up o pfc pwm gate drive, configurable either high or low true 78 p3.1/ aopwm2 i/o discrete programmable i/o or analog output 2 (pwm) 79 p3.2/int0 i/o discrete programmable i/o or external interrupt 0 80 p3.3/int1 i/o discrete programmable i/o or external interrupt 1 81 p3.4/t0 i/o discrete progra mmable i/o or timer/counter 0 input
irmcf312 33 pin number pin name internal ic pull-up /pull-down pin type description 82 p3.5/t1 i/o discrete progra mmable i/o or timer/counter 1 input 83 p3.6/rxd1 i/o discrete programmable i/o or 2 nd uart receive input 84 p3.7/txd1 i/o discrete programmable i/o or 2 nd uart transmit output 85 vss p digital common 86 vss p digital common 87 vdd1 p 3.3v digital power 88 p4.2/int5 i/o discrete programmable i/o or interrupt 5 89 p4.6/int9 i/o discrete programmable i/o or interrupt 9 90 scl/so-si i/o i 2 c clock output or spi data 91 sda/cs0 i/o i 2 c data or spi chip select 0 92 p5.1/tms i/o discrete progra mmable i/o or jtag test mode select 93 p5.2/tdo i/o discrete programma ble i/o or jtag port test data output 94 p5.3/tdi i/o discrete programma ble i/o or jtag test data input 95 tck i jtag test clock 96 tstmod 58 k ? pull down i test mode. must be tied to vss. factory use only 97 reset i/o reset, low true, schmitt trigger input 98 vdd2 p 1.8v digital power 99 pllvdd p 1.8v pll power. 100 pllvss p pll ground. table 22. pin list
irmcf312 34 9 package dimensions
irmcf312 35 10 part marking information irmcf312 ywwp xxxxxx ir logo production lot date code part number pin 1 indentifier order information lead-free part in 64-lead qfp moisture sensitivity rating ? msl3 part number order quantities irmcf312tr 1000 parts on tape and reel in dry pack the lqfp-100 is msl3 qualified this product has been designed and qualified for the industrial level qualification standards can be found at www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 252-7105 data and specifications subject to change wi thout notic e. 12/05/2006 www.irf.com

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